The present invention relates to a semiconductor memory device comprising a memory cell array having plural memory cells arranged in a matrix, and plural I/O data lines, and more particularly to its redundancy circuits.
The advancement of degree in the integration of semiconductor memories is notable, and in a dynamic random access memory (DRAM), a 1M bit capacity is in the mainstream. In such a large capacity random access memory, redundancy circuits are generally provided in order to lower the manufacturing cost. They dispose spare memory cells aside from the regular memory cells on the memory chip, and if a defect is found in part of the regular cells during a wafer inspection, the defective cells are replaced by the spare memory cells, thereby saving the defective chips. Practically, speaking within a memory array having plural memory cells arranged in a matrix, a spare row or a spare column for replacing the row or column containing defective memory cells, or both a spare row and a spare column are provided, and when the row address or column address of the row or column containing defective memory cells is selected, the row or column in the regular memory cell array is not selected, but the spare row or spare column is selected.
As another tendency accompanying the advancement of the degree of integration of semiconductor memory, diversification of bit organization is known. Conventionally, the DRAMs were used in a huge quantity as the main memory of a computer, it was enough with the .times.1 bit organization for accessing one memory cell each time. However, as the cost per bit is lowered, the application fields of DRAMs have been expanded, and the number of memory cells that can be integrated on one chip has greatly increased, and hence there is a growing demand for a multi-bit DRAM for accessing several memory cells at a time. As a multi-bit memory, at the present, the .times.4 bit organization is common in the DRAM, and the .times.8 bit organization in the static random access memory (SRAM), but henceforth it is expected that memories of .times.16 bit organization, .times.32 bit organization and even .times.64 bit organization will be required.
Examples of application of the conventional redundancy circuits in such multi-bit memory devices are shown in FIGS. 5 and 6. For the sake of simplicity, in FIGS. 5 and 6, the number of column addresses is four in .times.4 bit organization. Besides, the column lines and I/O data lines are actually composed of pairs of lines including the line for complementary data, but they are expressed by one line in these examples.
In FIG. 5, bit lines (column lines) possessing common column addresses are disposed adjacently. The bit lines B1, B2, . . . , B16 are regular bit lines. D1, D2, D3, D4 are I/O data lines corresponding of input/output data of 4 bits. Transistors T1, T2, . . . , T16 electrically connect the regular bit lines B1 to B16 to I/O data lines D1 to D4, according to the column selection signal lines C1, C2, C3, C4 decoded and activated by a regular column decoder 10. B17, B18, B19, B20 are spare bit lines, and if there is any defect in the memory cell on any of the regular bit lines B1 to B16 electrically connectable to the I/O data lines D1 to D4, such defective bit lines are replaced by spare bit lines B17 to B20. A redundancy column decoder 20 activates the redundancy column selection signal line C5 when the column address including the defective memory cell is selected. As a result, the transistors T17, T18, T19, T20 are made to conduct, and the spare bit lines B17 to B20 are electrically connected to the I/O data lines D1 to D4. At the same time, the column selection signal line to be activated by this column address if there is no defect in the regular memory cells remains inactive. The column address for activating the redundancy column selection signal line is set up by cutting off part of the fuse preliminarily formed on the chip by a laser after discovering the defective memory cell during a wafer inspection.
FIG. 6 is an example in which the bit lines electrically connected to the same I/O data line are disposed adjacently. As shown in FIG. 6, the regular bit lines B1, B2 . . . , B16 are disposed as being divided into four blocks for every corresponding I/O data line. In this case, the column decoders 10, 11, 12, 13 are disposed in each block, and according to the column address, one from each block of column selection signal lines C01, C02, C03, C04, C11, C12, C13, C14, C21, C22, C23, C24, C31, C32, C33, C34, for example, the column selection signal lines C01, C11, C21, C31 are activated. Spare bit lines B17, B18, B19, B20, and redundancy column decoders 20, 21, 22, 23 are also respectively disposed in each block. When the column address of the defective memory cell is selected, all of redundancy column selection signal lines C05, C15, C25, C35 are activated, and the transistors T17, T18, T19, T20 are made to conduct, and the spare bit lines B17, B18, B19, B20 are electrically connected to the I/O data lines D1, D2, D3, D4 respectively. At the same time, in each column decoder 10 to 13, the column selection signal line to be activated by the column address if there is no defect in the regular memory cells remains inactive.
Incidentally, the status of occurrence of defective memory cells is not completely random, but often adjacent memory cells become defective at the same time, or the adjacent bit lines are short-circuited to make two columns defective simultaneously. On the other hand, in the column redundancy circuit shown in FIG. 6, one bit line is replaced by the redundancy bit line in each block, and therefore if the adjacent upper and lower memory cells become defective at the same time, or the adjacent bit lines are short-circuited so as to be defective, it is impossible to save the memory device. Hence, the example shown in FIG. 6 is disadvantageous in that the efficiency of repair with this redundancy circuit is not as high as that of the example shown in FIG. 5.
By contrast, in FIG. 5, even if defective memory cells are present, spreading over two or more columns, it is possible to replace the cells with spare bit lines as long as they are in the range of the same column address. In the case of FIG. 5, however, since the transfer gate transistors T1, T2, . . . T20 for electrically connecting the bit lines to I/O data lines are disposed so as to overlap the I/O data lines D1 to D4, the layout design is restricted, and the chip area is larger than in FIG. 6. Instead of forming the transistors beneath the I/O data line wiring region, it may be possible to connect the drains of the transistors T1 to T20 to the I/O data lines D1 to D4 with the wiring crossing the I/O data lines D1 to D4, but in the case of FIG. 5, if the arrangement so structured, it is necessary to dispose one cross wiring for each bit line, and the wiring capacitance of the I/O data lines D1 to D4 increases significantly as compared with the case in which only one cross wiring is enough for each block, and the operating speed may be significantly lowered. Such problems of increased chip area and reduction of operating speed become more and more serious when the number of bits of input or output data increases.